1. Technical Field
The present invention relates to a scanning circuit of a display device and, in particular, to a scanning circuit including single conductivity type thin-film transistors.
2. Related Art
Display devices using amorphous silicon thin-film transistors (hereinafter referred to as “a-Si TFTs) have been used in a variety of applications ranging from compact panels such as mobile phone monitors to large panels such as personal computer monitors and large-sized thin-screen televisions. In general, a-Si TFTs have been used only in pixel arrays forming display regions, whereas integrated circuits (ICs) with large scale integration (LSI) have been used in gate driving circuits for driving pixels.
Recently, techniques for forming pixel arrays and gate driving circuits have been actively developed to save display production cost and reduce frame length (a distance from an outer periphery of a display to a display region). In order to form a gate driving circuit using single conductivity type transistors such as a-Si TFTs, a dynamic unit circuit is generally used, such as those disclosed in Patent Literature below.
A unit circuit of Patent Literature 1 (U.S. Pat. No. 5,222,082: FIG. 2, from line 37 of page 6 of the description) will be described with reference to FIG. 10. In FIG. 10, the unit circuit of Patent Literature 1 is an example of a dynamic unit circuit including single conductivity type transistors. When INPUT is high level, both transistors 18 and 21 are turned ON and nodes P1 and P2, respectively, are set to (VDD−Vth) and VSS, respectively. Herein, Vth is a threshold voltage of the transistors 18 and 21. Due to the potential increase of the P1, a transistor 16 is turned ON. In addition, since the P2 is VSS, the transistors 17 and 19 are OFF. Then, when INPUT goes low, the node P1 goes into a floating state. In this state, when a clock signal C1 changes from low level to high level, the potential of an OUTPUT 1 increases. At that time, the potential of the floating P1 also increases due to a boot strap effect via a not-shown parasitic capacitor between nodes P1 to 13 (OUTPUT 1) of the transistor 16. Accordingly, since the potential of the node P1 increases to a potential not less than the high level, a high voltage signal is applied to the gate of the transistor 16, whereby a high level clock signal C1 is transferred to the OUTPUT 1 without attenuation. When a clock signal C3 goes high, a transistor 20 is turned ON and thus the node P2 is set to (VDD−Vth). Herein, Vth is a threshold voltage of the transistor 20. As a result, since the transistors 17 and 19 are turned ON, the node P1 and the OUTPUT 1, respectively, are set to VSS to prevent circuit malfunction.
In the structure of Patent Literature 1, when the OUTPUT 1 is at low level, the transistors 17 and 19 are always ON to pull down the node P1 or the OUTPUT 1 to VSS. In other words, a high level voltage is applied to gate terminals of the transistors 17 and 19, whereas a low level voltage is applied to source or drain terminals thereof. This bias state is hereinafter referred to as “plus gate stress”. If the circuit is formed using a-Si TFTs, the “plus gate stress” causes a problem of increasing threshold voltage changes. In view of the problem of Patent Literature 1 above, the following solution has been disclosed.
A unit circuit of Patent Literature 2 (Japanese Unexamined Patent Application Publication No. H08-87897: FIG. 3 on page 6; from paragraph 0013) will be described with reference to FIG. 11. In FIG. 11, the unit circuit of Patent Literature 2 includes transistors 18, 25, 16, and 17 and a capacitor CB and is a dynamic unit circuit using ordinary single conductivity type transistors. When an input signal (a start signal or an OUTn-1 as a preceding-stage OUT signal) is input to the transistor 18, the potential of a node P1 increases from VSS to (VDD−Vth) and is charged to the capacitor CB, thereby bringing the transistor 16 into a conductive state. When the input section goes low and, in turn, a high level voltage of a clock signal is input to a terminal C1, the node P1 is brought into a floating state. At this time, since the transistor 16 is in the conductive state, the potential of an OUTn also goes up from VSS. In other words, since the potential of one of electrodes of the capacitor CB increases, the potential of the other electrode (the node P1) thereof also increases due to a boot strap effect. As a result, a high voltage gate signal is applied to the transistor 16 and a high level clock signal is transferred from the C1 terminal to the OUTn. At that time, the transistor 17, which has received an external voltage Vc1, is ON. However, since the transistor 17 is adapted to exhibit a lower current-driving performance than the transistor 16, the signal OUTn is output without being attenuated. After completion of the output operation, the signal OUTn is pulled down to VSS by the transistor 17. In other words, the transistor 17 is under the “plus gate stress” during most of the period of time (the present structure has a problem in terms of power consumption since through-current flows at the output).
A unit circuit of Patent Literature 3 (Japanese Unexamined Patent Application Publication No. 2006-351171: FIG. 5 on page 18; from paragraph 0036) will be described with reference to FIG. 12. As with FIG. 11, the circuit is also a dynamic unit circuit using single conductivity type transistors. In the circuit structure, a transistor pair (T3 and T4) maintaining a node J1 at low level (Voff), a transistor (T8) maintaining a node J2 at low level, a transistor (T11) maintaining a node J3 at low level, and a transistor pair (T5 and T6) maintaining OUT at low level have gates controlled by a clock signal LCLK1 or LCLK2. In other words, the transistors are under “plus gate stress” at a duty of 50% and a voltage level of the LCLK1 (LCLK2) (the same level as an output signal).